计数器|-电子技术精品网

PS1：这两天写论文写的晕头转向，越想越没有意思，早知道就开个跟自己关系大点的题目，那样也可以为将来的工作多打点基础，没办法，有时间也不能把以前的东西给丢了啊，这样相互补充着学吧，再说了，既然是跟编程有关的，那最后就肯定得落实到实现上，所以自己看再多也没有用，关键是自己能动手写出点东西了，那怕你写的乱七八糟，那也是有自己的想法。

PS2:今天心情有点糟，呵呵，怎么能这样，不知道自己应不应该坚持下去

非常谢谢riple!

//2006 BY JR

// 一个计数器有时间再把注释加上吧人的大脑是最不可靠的东西，呵呵

// 一个四位的计数器，在火龙刀上运行正常。主要是熟悉FPGA开发板的引脚定义设置，阅读开发板文档

module led(clk,load,addr,datain,A,B,C,D,E,F,G,H,A0,A1,A2,A3,EN);

input clk,load;
input [1:0] addr;
input [7:0] datain;
output A,B,C,D,E,F,G,H,EN; //7段数码管及旁边的小数点
output A0,A1,A2,A3;
reg A,B,C,D,E,F,G,H;
reg A0,A1,A2,A3;
reg [7:0] LED0,LED1,LED2,LED3; //四个LED显示管
reg [1:0] shiftreg;
reg [17:0] count; //设置一个计数器，对系统时钟进行分频，不然计数太快
assign EN="0"; //定义初始状态

//write the register
always@(posedge clk)
begin
if(load)
case(addr)
2'b00: LED0<=datain;
2'b01: LED1<=datain;
2'b10: LED2<=datain;
default: LED3<=datain;
endcase
end

always@(posedge clk)
begin
count<=count 18'b1;
end

always@(posedge clk)
begin
if(count==18'b1)
shiftreg<=shiftreg 2'b1;
end
//chip select
always@(posedge clk)
begin
case (shiftreg)
2'b00:
begin
{A3,A2,A1,A0}<=4'b0001;
{A,B,C,D,E,F,G,H}<=LED0;
end

2'b01:
begin
{A3,A2,A1,A0}<=4'b0010;
{A,B,C,D,E,F,G,H}<=LED1;
end

2'b10:
begin
{A3,A2,A1,A0}<=4'b0100;
{A,B,C,D,E,F,G,H}<=LED2;
end

default:
begin
{A3,A2,A1,A0}<=4'b1000;
{A,B,C,D,E,F,G,H}<=LED3;
end
endcase
end
endmodule

//测试程序
module top(clk,A,B,C,D,E,F,G,H,A0,A1,A2,A3,EN);
input clk;
output A,B,C,D,E,F,G,H,A0,A1,A2,A3,EN;
reg load;
reg [1:0] addr;
reg [7:0] datain;
reg [3:0] number0,number1,number2,number3;
reg [7:0] temp0,temp1,temp2,temp3;

reg [25:0] count; //分频计数器

led led1(clk,load,addr,datain,A,B,C,D,E,F,G,H,A0,A1,A2,A3,EN);

always@(posedge clk) //26位是大体计算出来的，没有严格要求
count<=count 26'b1;

always@(posedge clk)
begin
if(count==26'b1)
begin
load<=1'b1;
datain<=temp0;
addr<=2'b00;
end
else
if(count==26'b11)
begin
load<=1'b1;
datain<=temp1;
addr<=2'b01;
end
else
if(count==26'b101)
begin
load<=1'b1;
datain<=temp2;
addr<=2'b10;
end
else
if(count==26'b111)
begin
load<=1'b1;
datain<=temp3;
addr<=2'b11;
end
else
load<=1'b0;
end
//个位计数器满9就清零
always@(posedge clk)
begin
if(count=={26{1'b1}})
begin
if(number0==4'b1001)
number0<=4'b0;
else
number0<=number0 4'b1;
end
end

//十位计数器
always@(posedge clk)
begin
if(count=={26{1'b1}}&&number0==4'b1001)
begin
if(number1==4'b1001)
number1<=4'b0;
else
number1<=number1 4'b1;
end
end
//百位计数器
always@(posedge clk)
begin
if(count=={26{1'b1}}&&number0==4'b1001&&number1==4'b1001)
begin
if(number2==4'b1001)
number2<=4'b0;
else
number2<=number2 4'b1;
end
end

// 千位计数器
always@(posedge clk)
begin
if(count=={26{1'b1}}&&number0==4'b1001&&number1==4'b1001&&number2==4'b1001)
begin
if(number3==4'b1001)
number3<=4'b0;
else
number3<=number3 4'b1;
end
end

always@(posedge clk)
begin
case(number0)
4'b0000: temp0<=8'b000_00010;
4'b0001: temp0<=8'b100_11110;
4'b0010: temp0<=8'b001_00100;
4'b0011: temp0<=8'b000_01100;
4'b0100: temp0<=8'b100_11000;
4'b0101: temp0<=8'b010_01000;
4'b0110: temp0<=8'b010_00000;
4'b0111: temp0<=8'b000_11110;
4'b1000: temp0<=8'b000_00000;
4'b1001: temp0<=8'b000_01000;
default:temp0<=8'b000_00010;
endcase
end

always@(posedge clk)
begin
case(number1)
4'b0000: temp1<=8'b000_00010;
4'b0001: temp1<=8'b100_11110;
4'b0010: temp1<=8'b001_00100;
4'b0011: temp1<=8'b000_01100;
4'b0100: temp1<=8'b100_11000;
4'b0101: temp1<=8'b010_01000;
4'b0110: temp1<=8'b010_00000;
4'b0111: temp1<=8'b000_11110;
4'b1000: temp1<=8'b000_00000;
4'b1001: temp1<=8'b000_01000;
default:temp1<=8'b000_00010;
endcase
end

always@(posedge clk)
begin
case(number2)
4'b0000: temp2<=8'b000_00010;
4'b0001: temp2<=8'b100_11110;
4'b0010: temp2<=8'b001_00100;
4'b0011: temp2<=8'b000_01100;
4'b0100: temp2<=8'b100_11000;
4'b0101: temp2<=8'b010_01000;
4'b0110: temp2<=8'b010_00000;
4'b0111: temp2<=8'b000_11110;
4'b1000: temp2<=8'b000_00000;
4'b1001: temp2<=8'b000_01000;
default:temp2<=8'b000_00010;
endcase
end

always@(posedge clk)
begin
case(number3)
4'b0000: temp3<=8'b000_00010;
4'b0001: temp3<=8'b100_11110;
4'b0010: temp3<=8'b001_00100;
4'b0011: temp3<=8'b000_01100;
4'b0100: temp3<=8'b100_11000;
4'b0101: temp3<=8'b010_01000;
4'b0110: temp3<=8'b010_00000;
4'b0111: temp3<=8'b000_11110;
4'b1000: temp3<=8'b000_00000;
4'b1001: temp3<=8'b000_01000;
default:temp3<=8'b000_00010;
endcase
end

endmodule