以太网帧的校验和是用什么算法生成的？



标准的CRC生成式

`define CRC_INIT_VALUE (32'hFFFF_FFFF)

`define CRC_IDLE  (2'b00)

`define CRC_RUN   (2'b01)

`define CRC_STOP  (2'b11)



module crc_gen (

  compute_crc,

  data,

  clk,

  reset_n,

  crc

  );



input compute_crc;

input [3:0] data;

input clk;

input reset_n;

output [3:0] crc;



reg [1:0] state_crc;

reg [31:0] crc_buffer;

reg [2:0] crc_end;



function [31:0] count_crc; // the first serial data bit is d [0]

input [3:0] d;

input [31:0] c;

reg [31:0] new_crc;

begin

  new_crc[0] = d[3] ^ c[28];

  new_crc[1] = d[2] ^ d[3] ^ c[28] ^ c[29];

  new_crc[2] = d[1] ^ d[2] ^ d[3] ^ c[28] ^ c[29] ^ c[30];

  new_crc[3] = d[0] ^ d[1] ^ d[2] ^ c[29] ^ c[30] ^ c[31];

  new_crc[4] = d[0] ^ d[1] ^ d[3] ^ c[0] ^ c[28] ^ c[30] ^ c[31];

  new_crc[5] = d[0] ^ d[2] ^ d[3] ^ c[1] ^ c[28] ^ c[29] ^ c[31];

  new_crc[6] = d[1] ^ d[2] ^ c[2] ^ c[29] ^ c[30];

  new_crc[7] = d[0] ^ d[1] ^ d[3] ^ c[3] ^ c[28] ^ c[30] ^ c[31];

  new_crc[8] = d[0] ^ d[2] ^ d[3] ^ c[4] ^ c[28] ^ c[29] ^ c[31];

  new_crc[9] = d[1] ^ d[2] ^ c[5] ^ c[29] ^ c[30];

  new_crc[10] = d[0] ^ d[1] ^ d[3] ^ c[6] ^ c[28] ^ c[30] ^ c[31];

  new_crc[11] = d[0] ^ d[2] ^ d[3] ^ c[7] ^ c[28] ^ c[29] ^ c[31];

  new_crc[12] = d[1] ^ d[2] ^ d[3] ^ c[8] ^ c[28] ^ c[29] ^ c[30];

  new_crc[13] = d[0] ^ d[1] ^ d[2] ^ c[9] ^ c[29] ^ c[30] ^ c[31];

  new_crc[14] = d[0] ^ d[1] ^ c[10] ^ c[30] ^ c[31];

  new_crc[15] = d[0] ^ c[11] ^ c[31];

  new_crc[16] = d[3] ^ c[12] ^ c[28];

  new_crc[17] = d[2] ^ c[13] ^ c[29];

  new_crc[18] = d[1] ^ c[14] ^ c[30];

  new_crc[19] = d[0] ^ c[15] ^ c[31];

  new_crc[20] = c[16];

  new_crc[21] = c[17];

  new_crc[22] = d[3] ^ c[18] ^ c[28];

  new_crc[23] = d[2] ^ d[3] ^ c[19] ^ c[28] ^ c[29];

  new_crc[24] = d[1] ^ d[2] ^ c[20] ^ c[29] ^ c[30];

  new_crc[25] = d[0] ^ d[1] ^ c[21] ^ c[30] ^ c[31];

  new_crc[26] = d[0] ^ d[3] ^ c[22] ^ c[28] ^ c[31];

  new_crc[27] = d[2] ^ c[23] ^ c[29];

  new_crc[28] = d[1] ^ c[24] ^ c[30];

  new_crc[29] = d[0] ^ c[25] ^ c[31];

  new_crc[30] = c[26];

  new_crc[31] = c[27];

  count_crc = new_crc;

end

endfunction



assign crc [3] = ~ crc_buffer [28];

assign crc [2] = ~ crc_buffer [29];

assign crc [1] = ~ crc_buffer [30];

assign crc [0] = ~ crc_buffer [31];



always @(posedge clk or negedge reset_n)

  if (!reset_n)

    state_crc <= `CRC_IDLE;

  else 

    case (state_crc)

      `CRC_IDLE  : if (compute_crc)

                     begin

                       state_crc <= `CRC_RUN;

                       crc_buffer <= count_crc (data,`CRC_INIT_VALUE);

                     end

                   else

                     begin

                       state_crc <= `CRC_IDLE;

                       crc_buffer <= 32'h0000_0000;

                       crc_end <= 3'd0;

                     end

      `CRC_RUN   : if (!compute_crc)

                     begin

                       state_crc <= `CRC_STOP;

                       crc_buffer <= crc_buffer << 4;

                     end

                   else

                     begin

                       state_crc <= `CRC_RUN;

                       crc_buffer <= count_crc (data,crc_buffer);

                     end

      `CRC_STOP  : if (crc_end == 3'd6)

                   begin

                     state_crc <= `CRC_IDLE;

                     crc_buffer <= 32'h0000_0000;

                   end

                   else

                   begin

                     state_crc <= `CRC_STOP;

                     crc_buffer <= crc_buffer << 4;

                     crc_end <= crc_end   1'b1;

                   end

    endcase



endmodule